The classic problem with sensing a bipolar random access memory is the high capacitance present along the bit lines. The total capacitance presented to the bit line is a function of the number of cells along the column to be read. Every cell along the column has at least one emitter tied to the bit line. So if 64 cells are tied to the column line, 64 emitters are tied to that column line. In most static memory cells, the emitter is heavily doped and the base is heavily doped, so that the emitter base capacitance is high. Assuming 64 cells on a column, 63 have reversed biased base-emitter junctions, resulting in very high bit line capacitance. All of this capacitance has to be charged and discharged to sense what is stored in a selected cell.
A static memory cell includes two transistors which have opposite states. Reading the state of a given cell is a function of the sense circuit's ability to sense the voltage difference between bit lines tied to the emitters of the separate transistors which form a single cell. The only way to rapidly charge and discharge the capacitance of the transistors tied to the bit line to sense the cell state is with current; the higher the current the faster rate of charge and discharge.
However, cells classically cannot handle a high level of current. Too much current overloads the cell, so that the cell cannot be sensed or it is extremely difficult to sense. Due to the limitations imposed on the sensing current, one of the greatest sources of delay in bipolar memory arrays is the time required to discharge the bit lines. This may amount to as much as 50% of the total delay in reading a bipolar memory cell.
Therefore, the primary problem addressed by this invention is to provide a circuit arrangement and method for charging and discharging the capacitance tied to the bit lines very fast in order to maximize the speed with which a bipolar memory array can be read.